DRAM chips are well known in the art. One example is disclosed by Robert J. Proebsting and Robert S. Green in U.S. Pat. No. 3,969,706. This patent discloses a MISFET dynamic RAM chip wherein information from an address row are read and transferred to a column register. One bit in the column register is then selected by the column address decoder so that data is transferred from that bit to a data output latch. Upon completion of the row address strobe cycle, each cell in the address row is automatically refreshed by the data in respective bit positions of the column register. The state of the data output latch remains valid until a subsequent column address strobe is received. Read, write and read-modify-write cycles are supported. The entire system is substantially dynamic in operation which results in very low power consumption characteristic of DRAMs.
U.S. Pat. No. 4,422,160 to Hiroshi Watanabe discloses a memory device comprising an array of memory cells, a row decoder, a column decoder, and a shift register in parallel with the column decoder. Shift operation of the shift register is effected at each time the column strobe signal CAS is active during the active level state of the row address strobe signal RAS. The Watanabe memory device provides both high-speed operation and low power consumption.
Also known in the art are shift register circuits having each stage comprised of a master circuit and a slave circuit. One example is disclosed by Robert J. Scavuzzo in U.S. Pat. No. 4,386,282. This patent discloses emitter function logic (EFL) shift register circuits having right and left shift capability, asynchronous set and clear, and asynchronous parallel load capability. Other examples of master/slave circuits are disclosed in U.S. Pat. No. 4,359,647 to Wolfgang Trinkl and U.S. Pat. No. 4,356,411 to Yosoji Suzuki and Minoru Takada.
The above-referenced application Ser. No. 06/393,996 by F. H. Dill discloses a dynamic RAM (DRAM) having a second data transfer port which is provided to improve the efficiency of data transfer to and from the memory. Dill provides an internal row buffer register connected in parallel with the RAM sense amplifiers. When a row is addressed and a read transfer pulse is applied to the register, the row word transfer to the row buffer register is completed. A subsequent signal applied to the row buffer shift register will clock the contents of the register to a second input/output port. One application for the Dill dynamic RAM is in a bit map display device wherein the second output port is used to supply the refresh data to a CRT display. The primary input/output port is then used to update the memory with new pixel data for later display without incurring delays from tying up the primary input/output port with refresh information for the display. Examples of such bit map displays are disclosed in applications Ser. No. 06/394,044 by F. H. Dill et al and Ser. No. 616,047, by R. E. Matick et al referenced above.